Redundancy architectures and techniques are widely used to improve the yield of random access memory (RAM) devices, such as static RAMs, as but one example. In a typical RAM redundancy arrangement, a fuse element can be placed in series with each word line of a memory array. When a memory cell is determined to be defective, a fuse for the corresponding row can be “blown” (typically causing an open circuit), to thereby de-couple an address decoder from the row incorporating the defective memory cell.
The address of the row having the defective memory cell can be programmed into a spare (redundant) address decoder coupled to a redundant row. Thus, in a subsequent read or write operation, an access directed to the row containing the defective memory cell can be re-directed to the redundant row.
While such conventional redundancy techniques can benefit RAM devices, such approaches are generally not feasible in content addressable memory (CAM) devices.
Unlike RAM devices, CAM devices can include locations that are addressed in response to the content stored, rather than a physical address of the array. Thus, in many conventional arrangements, in a compare (i.e., search) operation, a CAM device can receive a compare data value (i.e., comparand) that is compared to all data values stored within the entries (e.g., rows) of one or all CAM arrays within the CAM device. According to a comparison result, each CAM entry can assert or de-assert an associated match signal. Match results can be provided on match lines coupled to a priority encoder. A priority encoder can translate a matching entry into a matching address or CAM index for output from a CAM device.
Conventionally, each row of a CAM array can be connected to a word line in order to allow data values to be read from and written to the row, as well as a match line that can reflect a match result for such a row.
CAM devices can come in a variety of forms. A binary CAM device can provide bit-by-bit matching between an applied compare data value and values stored within the CAM entries. While appropriate for some applications, it may not always be desirable to match all bits between a compare data value and a stored data value.
A currently more useful type of CAM device is the ternary CAM (or TCAM) device. A TCAM device can provide selective masking of bit compare operations between a compare data value and the stored data values. Accordingly, each entry can be conceptualized as including a stored data value as well as a mask value that can indicate which bits of the stored data value will take place in a compare operation. For example, in some conventions, a mask bit of “one” can indicate that the corresponding bit of a stored data value is to be compared against the corresponding bit of an applied compare data value. In contrast, a mask bit of “zero” can indicate that the corresponding bit of a stored data value is not to be compared against the corresponding bit of an applied compare data value. Such a masked bit is typically forced to provide a “match” result, thus preventing the masked bit from generating a mismatch indication even if the bit value differs from the compare data bit value.
TCAM devices can take various forms. A “full” TCAM device can provide a mask bit for every stored data bit. That is, in a full TCAM device, each separate memory location can be conceptualized has having its own mask field and data field. Thus, in a full TCAM device, each stored mask controls the masking of match operations for exactly one stored data value. Such an arrangement can provide great flexibility in the type of searches performed, but at the cost of considerable circuit size. As a result, full TCAM devices can be relatively high in cost.
One way to provide masking capabilities, and yet not require as much circuit area as a full TCAM device, is to employ a “pseudo” TCAM (PTCAM) device. In a PTCAM device, mapping between a mask and stored data values can be 1:N, where N>1. That is, one mask field can provide mask data to multiple stored data values. This is in contrast to a full TCAM device that is understood to provide 1:1 mapping between mask and stored data values.
To better understand various aspects of the disclosed embodiments, conventional PTCAM devices and redundancy techniques will now be described.
FIG. 10 shows is a general view illustrating a conventional PTCAM device structure. A conventional PTCAM device can include a number of sections (or blocks), one of which is shown as 1000. As shown, each section 1000 can include a mask entry 1002 and a number of PTCAM entries 1004. In the example shown, there is one mask entry per eight PTCAM entries. As represented by the arrows of FIG. 10, a mask entry 1002 can provide mask data to all eight PTCAM entries 1004.
To try to increase yield in the event of defects in a PTCAM device, redundancy techniques have been employed. FIG. 11 shows one conventional approach to implementing redundancy in a PTCAM device. In the conventional arrangement shown, a PTCAM device 1100 can include a number of standard blocks 1102-0 to 1102-63, each of which includes one mask entry, formed by an array of 1×72 static random access memory (SRAM) cells, and eight PTCAM entries, formed in an array of 8×72 PTCAM cells. Also included is one redundant block 1104 that includes one redundant mask entry, formed by an array of 1×72 static random access memory (SRAM) cells, and eight redundant PTCAM entries, formed in an array of 8×72 PTCAM cells.
In the above conventional arrangement, redundancy is implemented on a block-by-block basis. That is, if one row within a standard block (1102-0 to 1102-63) is defective, the entire block is replaced by redundant block 1104. In such an approach, one row of redundant SRAM cells and eight rows of redundant PTCAM cells are used to replace only one defective row (either SRAM or PTCAM). As a result, if only one PTCAM row is defective, seven out of 512 rows of PTCAM cells are wasted. This can result in a waste (or penalty) within an array of about 1%.
In light of the above, it would be desirable to arrive at some way of providing row redundancy in a more space efficient manner than the above conventional approach.